• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated electronic circuit comprising a protection device (DIS) comprising a metal shield (BCL) made in its interconnection part (INT), and detection means (3) comprising the metal shield (BCL) and configured to detect a presence an external electromagnetic radiation representative of an attack by injection of faults.
    公开号:FR3053503A1
    申请号:FR1656233
    申请日:2016-06-30
    公开日:2018-01-05
    发明作者:Thomas Ordas；Alexandre Sarafianos；Fabrice Marinet；Stephane Chesnais
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    ® FRENCH REPUBLIC
    NATIONAL INSTITUTE OF INDUSTRIAL PROPERTY
    COURBEVOIE © Publication number:
    (to be used only for reproduction orders) (© National registration number
    053 503
    56233 © Int Cl 8 : G 06 K 19/073 (2017.01)
    PATENT INVENTION APPLICATION
    A1
    ©) Date of filing: 30.06.16. © Applicant (s): STMICROELECTRONICS (ROUS- (30) Priority: SET) SAS Simplified joint stock company - FR. @ Inventor (s): ORDAS THOMAS, SARAFIANOS ALEXANDRE, MARINET FABRICE and CHESNAIS STE- (43) Date of public availability of the PHANE. request: 05.01.18 Bulletin 18/01. ©) List of documents cited in the report preliminary research: Refer to end of present booklet (© References to other national documents ® Holder (s): STMICROELECTRONICS (ROUSSET) related: SAS Simplified joint-stock company. ©) Extension request (s): © Agent (s): CASALONGA & ASSOCIES.
    METHOD FOR PROTECTING AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT.
    Integrated electronic circuit comprising a protection device (DIS) comprising a metal shield (BCL) produced in its interconnection part (INT), and detection means (3) comprising the metal shield (BCL) and configured to detect a presence of external electromagnetic radiation representative of a fault injection attack.
    FR 3 053 503 - A1
    i
    Method for protecting an integrated circuit, and corresponding integrated circuit
    Modes of implementation and embodiment of the invention relate to integrated circuits, and more particularly the protection of integrated circuits against attacks by injection of faults (DFA, "Differential Fault Analysis" according to the well known Anglo-Saxon name skilled in the art), and particularly against attacks by injection of faults carried out using external electromagnetic radiation.
    Among the types of attack known to those skilled in the art, we can cite the probing attack ("probing" according to the Anglo-Saxon name), which involves the insertion of a probe into the interconnection part of a circuit in order to read the electrical signals emitted by the various components, then to analyze them in order to obtain information on the operation of the circuit.
    In order to protect against this type of attack, it is conventionally possible to place a protective shield in the upper zone of the interconnection portion of the circuit. The shield conventionally comprises metal tracks in which electrical signals are circulated. Thus, when the reading probe is inserted, the metal tracks are deteriorated and the signals can no longer circulate in the shield. The circuit can therefore detect an intrusion and for example generate an alarm signal so that an appropriate action can be taken.
    Another known type of attack is the attack by fault injection, which consists in injecting a fault for example by means of an electromagnetic injection coil generating electromagnetic radiation, so as to modify for example the value of one or more bits of temporary result of a calculation without deteriorating the physical integrity of the circuit.
    An analysis of the behavior of the circuit in response to these injections can make it possible to obtain secure information such as for example encryption keys.
    There are ways to protect yourself against this type of attack, such as cryptographic calculations including multiple verifications of the calculations made.
    However, these methods can be circumvented by more sophisticated fault injection methods, such as double fault injection attacks.
    Thus, according to one embodiment, it is proposed to protect in a material and simple manner an integrated circuit against attacks by injection of electromagnetic faults.
    According to one aspect, a method is proposed for protecting an integrated circuit against attack by injection of faults using external electromagnetic radiation, said integrated circuit comprising a metal shield produced in its interconnection part.
    According to a general characteristic of this aspect, the method comprises detection via the metal shield of said electromagnetic radiation.
    Thus, a shield generally present is advantageously used for protection against probing attacks (“probing”) for the detection of an electromagnetic field capable of generating an injection of faults in the circuit.
    According to one embodiment, the detection comprises a placement of the shield in a receiving antenna configuration and a detection of at least one signal greater than a threshold circulating in the shield.
    An electromagnetic field capable of generating fault injection is in practice a field having an intensity greater than a threshold which results in the circulation of a signal greater than a threshold in the shield.
    And this threshold, which depends on each circuit, can for example be determined during a characterization phase of the integrated circuit using an electromagnetic test injection coil capable of generating electromagnetic test radiation having adjustable values. .
    An adjustment of the detection sensitivity comprising a connection of a variable resistance to the metal shield can be implemented.
    Prior to said detection, a verification of the integrity of the metal shield can be carried out, which includes checking for a possible interruption in the flow of current in the shield.
    According to another aspect, an integrated circuit is proposed comprising a protection device comprising a metal shield produced in its interconnection part.
    According to a general characteristic of this other aspect, the circuit comprises detection means comprising the metal shield and are configured to detect the presence of external electromagnetic radiation representative of a fault injection attack.
    An electromagnetic field representative of a fault injection attack conventionally corresponds to an electromagnetic pulse whose amplitude reaches or exceeds a predetermined threshold, which can vary from one circuit to another.
    The detection means may include first control means able to place the shield in a receiving antenna configuration, an interface module coupled to the shield and configured to detect a first electrical signal circulating in the antenna and deliver a first signal control, and control means configured to receive the first control signal.
    According to one embodiment, the integrated circuit includes verification means configured to verify the integrity of the shield.
    The verification means can comprise second control means configured to transmit a second electrical signal to an input of the shield and the interface module can be configured to detect the presence of the second electrical signal at the output of the shield and deliver a second signal control, and the control means are configured to receive the second control signal.
    The integrated circuit may also include a control stage configurable by the control means and forming in a first configuration the first control means and in a second configuration the second control means.
    According to one embodiment, the metal shield comprises at least one metal track comprising a first end and a second end, and the configurable stage comprises a first transistor connected between the first terminal of the metal track and the ground, a generator configured to generating the second electrical signal, a transmission gate connected between the first terminal and the generator, and the control means configured to control the first transistor and the transmission gate, so that in the first configuration the first transistor is blocked and the transmission gate is in a conducting state, and in the second configuration the first transistor is conducting and the transmission gate is blocked.
    According to one embodiment, the interface module comprises a first flip-flop D comprising a first input connected to a supply terminal delivering a supply voltage, a first clock input connected to the second terminal, and a first output , and a second flip-flop D comprising a second input connected to the first output, a second clock input connected to a clock generator delivering a clock signal, and a second output configured to deliver the first or the second signal control respectively on receipt of the first or second electrical signal on the first input.
    The shield may further comprise adjustment means configured to vary the electrical resistance of said shield, and / or protection means connected to said metal track and configured to protect the integrated circuit against overvoltages.
    The shield may include a plurality of metal tracks.
    According to another aspect, a system is proposed comprising an integrated circuit as described above, the system possibly being a smart card or a computer system.
    Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiments, in no way limiting, and the attached drawings in which
    - Figures 1 to 5 illustrate embodiments of the invention.
    FIG. 1 illustrates an example of an integrated circuit CI comprising a protection device DIS, and FIG. 2 is a sectional view along the section line II-II of FIG. 1.
    The integrated circuit CI comprises a semiconductor substrate 1, in which a plurality of components 10 has been produced.
    The components here in particular include logic gates forming for example a CRY cryptographic circuit intended in particular for carrying out operations in a secure manner.
    The substrate 1 is surmounted by an interconnection region INT (known by a person skilled in the art under the acronym BEOL: “Back End Of Line”), comprising several metal levels each comprising one or more metal tracks 11 coated in an insulating material 12 (“Intermetal dielectric” according to the Anglo-Saxon name well known to those skilled in the art).
    Some of the metal tracks 11 of the metal levels are interconnection tracks connecting together at least some of the components 10 of the cryptographic circuit CRY by means of vias (not shown in the figures for simplification purposes).
    Other metal tracks can conventionally be tracks for redistribution of the supply voltage Vdd of the integrated circuit CI, or connected to ground GND.
    The integrated circuit in this example comprises six metallization levels. Level six N6 of metallization, which is here the highest level, comprises a BCL shield which here comprises several parallel metal tracks arranged so as to form a rectangular spiral. The ends of each metal track of the spiral are not directly coupled via vias to components of the CRY cryptographic circuit, but as will be seen ci3053503 after verification means 2 and detection means 3 produced in and on the substrate 1.
    The BCL shield, the verification means 2 and the detection means 3 are here part of the protection device DIS.
    The verification means 2 are configured to generate an electrical signal in each metal track and to receive this electrical signal in order to verify the physical integrity of the shield. Thus, in the event of a sample attack, the metal tracks are cut by the probe and the verification means no longer receive the signal generated. Control means 4 can then generate an alarm signal. The circuit is therefore protected against probing attacks.
    The detection means 3 are configured to detect the electrical signals induced in the shield by an external electromagnetic field or radiation, and to send if necessary a signal to the control means 4 of the circuit. In response to this signal, the control means 4 can also generate an alarm signal.
    In this example, the control means 4 are produced by a logic circuit produced in the substrate 1 of the integrated circuit CI. However, it would be possible to implement the control means 4 in software for example within a microcontroller.
    Thus, the BCL shield is used in this case as a receiving antenna, and is able to detect a particularly intense electromagnetic field generated by an electromagnetic injection coil used for example during an attack by electromagnetic fault injection.
    The integrated circuit CI therefore here comprises two protection systems protecting it against two different types of attack, using a common means, namely the BCL shield. This is particularly advantageous in terms of manufacturing process and production cost.
    FIG. 3 is a schematic representation from the electrical point of view of a protection device DIS according to an embodiment of the invention, which comprises the verification means 2 and the detection means 3.
    In this embodiment, the BCL shield comprises a single metal track 6.
    The detection means 3 comprise the BCL shield, an interface module 5, the control means 4, and a configurable control stage CMD configured in a first configuration to form first control means.
    The verification means 2 comprises the shield BCL, the interface module 5, the control means 4, and the configurable stage CMD configured in a second configuration to form second control means.
    The control means 4 are configured to place the configurable stage CMD in its first configuration or in its second configuration on the basis of logic control signals SCI, SC2, and SC3.
    The configurable CMD stage here includes a transmission door 20 ("Path spoils" according to the English name well known to those skilled in the art) electrically connected to a first end of the BCL shield, or first terminal 60.
    The transmission gate 20 conventionally comprises an NMOS transistor TRI and a PMOS transistor TR2, having their sources mutually electrically connected and their drains mutually electrically connected.
    The transmission door 20 has the advantage of being particularly reliable, but any other type of switch could have been envisaged here.
    The drains of the TRI and TR2 transistors are coupled to the first terminal 60, and the sources of the TRI and TR2 transistors are coupled to signal generation means 7, here for example a current source.
    Here, the control means 4 are coupled to the gates of the transistors TRI and TR2 and therefore control the transmission gate 20 by means of the signals SCI and SC2, the signal SC2 being the signal complementary to the signal SCI.
    Thus, in order to make the transmission gate 20 passable, and therefore to transmit a first signal SI generated by the signal generation means 7 to the metal track 6, the signal SCI, here a non-zero potential, is applied by the means control 4 to the gate of the NMOS transistor TRI and the signal SC2, here a zero potential, is applied by the control means 4 to the gate of the PMOS transistor TR2.
    The configurable stage CMD further comprises a third transistor TR3 coupled between the first terminal 60 and the ground GND, and controlled by the signal SC3 of the control means 4.
    The interface module 5 comprises a first flip-flop "D" conventionally comprising a first data input Dl, a first clock input Cl, and a first output Ql, and a second flip-flop "D" 51 comprising a second data input D2, a second clock input C2 and a second output Q2.
    For each appearance of front on their respective clock input C1 and C2, the flip-flops 50 and 51 copy their respective data input Dl and D2 onto their respective output Ql and Q2.
    The first clock input Dl of the first flip-flop 50 is coupled to the second terminal 61 of the metal track 6, and the first data input Dl is coupled to a supply terminal of the integrated circuit CI, which delivers the signal Vdd .
    The second data input D2 is coupled to the first output Ql of the first flip-flop 50 and the second clock input C2 is coupled to a clock signal generator (not shown) delivering a CLK signal, for example the generator of clock signal used to clock the secure operations of the CRY cryptographic circuit. The second output Q2 of the second flip-flop is coupled to the control means 4 of the integrated circuit CI.
    Thus, when a signal appears on the first clock input C1, the signal Vdd is copied to the first output Ql and transmitted to the second input D2. At each edge of the clock signal
    CLK, the signal Vdd is therefore also copied to the second output Q2 and transmitted to the control means 4.
    The signal Vdd at the output of the interface module 5 can therefore be considered as a CTR control signal.
    Thus, thanks to the second flip-flop 51, the interface module 5 advantageously delivers the control signal CTR synchronously, that is to say on the appearance of a clock front.
    As seen above, the device DIS has a configurable control stage CMD comprising the third transistor TR3 and the transmission gate 20, and the configurable stage CMD can be configured in its first configuration or in its second configuration by to the control signals SCI, SC2 and SC3.
    In the first configuration, the third transistor TR3 is blocked by the application of the signal SC3 on its gate, for example here a zero potential. This configuration allows you to verify the physical integrity of the BCL shield.
    To this end, a first signal SI is transmitted to the first terminal 60 by the generation means 7 and the transmission gate 20. For example, the signal SI can be a current pulse, of Dirac type, generated by a very short in the passing state of the transmission door 20.
    If the metal track 6 is sectioned, that is to say for example if a test attack has taken place, the first signal SI is not transmitted to the interface module 5 which therefore does not transmit the voltage Vdd, or CTR control signal, to the control means 4. In this first configuration, the control means 4 are configured to generate an alarm signal in the absence of the CTR control signal.
    If the metal track 6 is not sectioned, that is to say if no probe attack has taken place, the first signal SI is indeed transmitted to the interface module 5 which sends the control signal CTR to the control means 4, which therefore do not generate an alarm signal.
    ίο
    In the second configuration, the transmission gate 20 is blocked and the third transistor TR3 is on. The first terminal 60 of the metal track 6 is therefore connected to ground GND.
    Thus, in this second configuration, the metal track 6 behaves like a receiving antenna. In the event of an attack by electromagnetic fault injection, that is to say in the presence of a particularly intense electromagnetic field through the BCL shield, a current is generated in the metal track 60 and transmitted to the interface module 5 The interface module 5 then sends the control signal CTR to the control means 4, which in this second configuration generate an alarm signal.
    Conventionally at the start of the integrated circuit CI, the device DIS is in the first configuration, and passes into the second configuration once the verification has been carried out.
    The DIS device also comprises adjustment means 8 making it possible to adjust the sensitivity of the detection means 3.
    The adjustment means 8 here comprise a plurality of transistors TR4, TR5, and TR6 coupled in parallel between the ground GND and the second terminal 61.
    The transistors are controlled by the control means 4 via signals SC4, SC5 and SC6. Depending on the desired sensitivity, the control means 4 put one or more transistors into the on state. The adjustment means 8 therefore act here as a variable resistance.
    Thus, by adjusting the resistance value, the potential on the second terminal 61 resulting from the presence of an electromagnetic field of given intensity also varies.
    In other words, the interface module 5 is triggered only from a certain potential value on the first clock input C1, and therefore on the second terminal 61, the adjustment means 8 make it possible to define a detection threshold for the DIS device.
    The detection threshold value is obtained during a characterization phase of the DIS device, by voluntarily carrying out fault injection attacks using an electromagnetic injection coil emitting electromagnetic pulses of different amplitudes, and by determining a threshold amplitude from which the pulse allows fault injection.
    The resistance of the BCL shield is then adjusted so that fields of amplitude lower than the threshold amplitude do not trigger the interface module.
    The detection threshold is therefore specific to each circuit.
    This is particularly advantageous when the integrated circuit CI is used in an environment comprising electromagnetic disturbances, for example near other electronic devices, so that the detection means 3 are not triggered by said disturbances but only by an electromagnetic attack.
    The DIS device further comprises protection means 9 configured to protect the DIS device against overvoltages.
    Indeed, during a fault injection attack, the intensity of the electromagnetic field generated by the injection coil is not predictable, and it is possible that too large currents are generated in the DIS device, which may damage the circuit.
    The protection means 9 comprise two pairs of diodes 90 and 91.
    The first pair of diodes 90 comprises a first diode DI and a second diode D2 connected in series, the anode of the first diode DI being connected to the first terminal 60 and the cathode of the second diode D2 being connected to the terminal of supply of the integrated circuit delivering the Vdd signal.
    The second pair of diodes 91 comprises a third diode D3 and a fourth diode D4 connected in series, the anode of the third diode D3 being connected to ground GND and the cathode of the fourth diode D4 being connected to the second terminal 61.
    The integrated electronic circuit CI described above and illustrated in FIGS. 1 to 3 can conventionally be integrated into a system comprising a processing unit, conventionally in a processing unit of a smart card, a computer, or a terminal mobile telephony, which require the implementation of secure operations.
    FIGS. 4 and 5 illustrate computer systems comprising secure processing units in which integrated circuits IC are produced according to an embodiment of the invention. FIG. 4 illustrates a smart card CP and FIG. 5 illustrates a portable computer CMP. The smart card CP and the portable computer CMP comprise for example a microprocessor comprising an integrated circuit according to an embodiment of the invention.
    The examples of application of the invention are not limited to those illustrated in FIGS. 4 and 5, and a person skilled in the art will know how to apply the embodiments and embodiments of the invention described above and illustrated in the figures. 1 to 3 to other known systems.
    The modes of implementation and embodiment presented here are in no way limiting. In particular, although an integrated circuit comprising a single device has been described previously, it would be entirely possible to envisage an integrated circuit comprising several secure modules produced in the substrate, each of these modules being associated with a protection device. distinct with the shield made above the module.
    And, although the electrical diagram of a DIS device comprising a single metal track 6 has been described, it should be noted that in the case of a device comprising a plurality of metal tracks, each of these tracks would be used in the first configuration as a means of verification, while in the second configuration one or more of them would be used as a receiving antenna.
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    1. Method for protecting an integrated circuit (IC) against attacks by fault injection using external electromagnetic radiation, said integrated circuit (CI) comprising a metal shield (BCL) made in its part interconnection (INT), characterized in that the method comprises detection via the metal shield (BCL) of said electromagnetic radiation.
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which the detection comprises placing the shield (BCL) in a receiving antenna configuration and detecting at least one signal greater than a threshold circulating in the shield (BCL).
    [3" id="c-fr-0003]
    3. Method according to any one of claims 1 and 2, comprising an adjustment of the detection sensitivity comprising a connection of a variable resistance to the metal shield (BCL).
    [4" id="c-fr-0004]
    4. Method according to one of claims 1 to 3, comprising prior to said detection, a verification of the integrity of the metal shield (BCL) comprising a control of a possible interruption of the flow of current in the shield ( BCL).
    [5" id="c-fr-0005]
    5. Integrated circuit comprising a protection device (DIS) comprising a metal shield (BCL) produced in its interconnection part (INT), characterized in that it comprises detection means (3) comprising the metal shield (BCL ) and configured to detect the presence of external electromagnetic radiation representative of a fault injection attack.
    [6" id="c-fr-0006]
    6. The circuit as claimed in claim 5, in which the detection means (3) comprise first control means (CMD) able to place the shield (BCL) in a receiving antenna configuration, an interface module (5) coupled to the shield (BCL) and configured to detect a first electrical signal flowing in the antenna and to deliver a first control signal, and control means (4) configured to receive the first control signal.
    [7" id="c-fr-0007]
    7. The circuit as claimed in claim 5 or 6, comprising verification means (2) configured to verify the integrity of the shield (BCL).
    [8" id="c-fr-0008]
    8. Circuit according to one of claims 6 and 7, in which the verification means (2) comprise second control means (CMD) configured to transmit a second electrical signal (SI) to an input of the shield (BCL), the interface module (5) configured to detect the presence of the second electrical signal (SI) at the outlet of the shield (BCL) and deliver a second control signal, and the control means are configured to receive the second control signal .
    [9" id="c-fr-0009]
    9. The circuit of claim 8, comprising a control stage (CMD) configurable by the control means (4) and forming in a first configuration the first control means and in a second configuration the second control means.
    [10" id="c-fr-0010]
    10. The circuit as claimed in claim 9, in which the metal shield (BCL) comprises at least one metal track (6) comprising a first terminal (60) and a second terminal (61), and in which the configurable stage (CMD) comprises a transistor (TR3) connected between the first terminal (60) of the metal track and the ground (GND), a generator (7) configured to generate the second electrical signal (SI), a transmission gate (20) connected between the first terminal (60) and the generator (7), and the control means (4) are configured to control the transistor (TR3) and the transmission gate (20), so that in the first configuration the transistor (TR3 ) is blocked and the transmission gate (20) is in a conducting state, and in the second configuration the transistor (TR3) is conducting and the transmission gate (20) is blocked.
    [11" id="c-fr-0011]
    11. Circuit according to any one of claims 6 to 10, in which the interface module (5) comprises a first flip-flop D (50) comprising a first input (Dl) connected to a supply terminal intended to deliver a supply voltage (Vdd), a first clock input (Cl) connected to the second terminal (61), and a first output (Ql), and a second flip-flop D (51) comprising a second input (D2) connected at the first output (Ql), a second clock input (C2) connected to a clock generator capable of delivering a clock signal (CLK), and a second
    5 output (Q2) configured to deliver the first or second control signal (CTR) respectively upon receipt of the first or second electrical signal on the first clock input (Cl).
    [12" id="c-fr-0012]
    12. Circuit according to any one of claims 5 to 11, in which the shield (BCL) further comprises means for
    10 setting (8) configured to vary the electrical resistance of said shield (BCL).
    [13" id="c-fr-0013]
    13. Circuit according to any one of claims 5 to 12, in which the device (DIS) further comprises protection means (9) at the shield (6) and configured to protect the device
    15 (DIS) against overvoltages.
    [14" id="c-fr-0014]
    14. Method according to any one of claims 5 to 13, wherein the shield (BCL) comprises several metal tracks.
    [15" id="c-fr-0015]
    15. System comprising an integrated circuit (IC) according to any one of claims 5 to 14.
    [16" id="c-fr-0016]
    16. The system of claim 15, the system being a smart card (CP) or a computer system (CMP).
    1/2
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    法律状态:
    2017-05-22| PLFP| Fee payment|Year of fee payment: 2 |
    2018-01-05| PLSC| Search report ready|Effective date: 20180105 |
    2018-05-25| PLFP| Fee payment|Year of fee payment: 3 |
    2020-03-13| ST| Notification of lapse|Effective date: 20200206 |
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    FR1656233|2016-06-30|FR1656233A| FR3053503B1|2016-06-30|2016-06-30|METHOD FOR PROTECTING AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT|
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    US15/446,472| US10361164B2|2016-06-30|2017-03-01|Integrated circuit protection method, and corresponding integrated circuit|
    CN201710132181.7A| CN107563191B|2016-06-30|2017-03-07|Method for protecting an integrated circuit and corresponding integrated circuit|
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